Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29556 )
Change subject: siemens/mc_apl4: Disable CLKREQ of PCIe root ports ......................................................................
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 6 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index f3e8a77..a2a2ba1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -6,11 +6,12 @@
register "sci_irq" = "SCIS_IRQ10"
- # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + # Disable all clkreq of PCIe root ports as SMARC interface do not + # have this pins. + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"