[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Calculate TSEG limit from registers

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46991 )

Change subject: nb/intel/haswell: Calculate TSEG limit from registers
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nb/intel/haswell: Calculate TSEG limit from registers

Done for consistency with other northbridges.

Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/northbridge/intel/haswell/memmap.c
1 file changed, 6 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 02d120b..c19cfec 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -4,13 +4,13 @@
 #define __SIMPLE_DEVICE__

#include <arch/romstage.h>
-#include <commonlib/helpers.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <security/intel/txt/txt_platform.h>
 #include <security/intel/txt/txt_register.h>
+#include <types.h>

#include "haswell.h"

@@ -19,9 +19,9 @@
    return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB);
 }

-static size_t northbridge_get_tseg_size(void)
+static uintptr_t northbridge_get_tseg_limit(void)
 {
-	return CONFIG_SMM_TSEG_SIZE;
+	return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB);
 }

union dpr_register txt_get_chipset_dpr(void)
@@ -62,7 +62,9 @@
 void smm_region(uintptr_t *start, size_t *size)
 {
    *start = northbridge_get_tseg_base();
-	*size = northbridge_get_tseg_size();
+	*size = northbridge_get_tseg_limit();
+
+	*size -= *start;
 }

void fill_postcar_frame(struct postcar_frame *pcf)