[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11943

-gerrit

commit 6c18d50564afd2879fa7065cb6ee8ee6afa87ec6
Author: Timothy Pearson 
Date:   Sat Sep 5 18:00:27 2015 -0500

northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations

Change-Id: I45eb03a4b351e458e8448245896743bd6fa57637
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdfam10/raminit_amdmct.c | 46 +++++++++++++++++++++++----
 src/northbridge/amd/amdmct/wrappers/mcti_d.c  |  2 +-
 2 files changed, 41 insertions(+), 7 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index a585fae..3f33eba 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -44,29 +44,58 @@ static  void print_tf(const char *func, const char *strval)
 #endif
 }

-static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
+static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq)
 {
    /* Return limited maximum RAM frequency */
    if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
-		if (IS_ENABLED(CONFIG_DIMM_REGISTERED)) {
+		if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
    		/* K10 BKDG Rev. 3.62 Table 53 */
    		if (count > 2) {
    			/* Limit to DDR2-533 */
    			if (freq > 266) {
    				freq = 266;
-					print_tf(__func__, ": More than 2 DIMMs on channel; limiting to DDR2-533\n");
+					print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n");
    			}
    		}
-		}
-		else {
+		} else {
    		/* K10 BKDG Rev. 3.62 Table 52 */
    		if (count > 1) {
    			/* Limit to DDR2-800 */
    			if (freq > 400) {
    				freq = 400;
-					print_tf(__func__, ": More than 1 DIMM on channel; limiting to DDR2-800\n");
+					print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n");
+				}
+			}
+		}
+	} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+		if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
+			/* K10 BKDG Rev. 3.62 Table 34 */
+			if (count > 2) {
+				/* Limit to DDR3-800 */
+				if (freq > 400) {
+					freq = 400;
+					print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR3-800\n");
+				}
+			} else if (count == 2) {
+				/* Limit to DDR3-1066 */
+				if (freq > 533) {
+					freq = 533;
+					print_tf(__func__, ": 2 registered DIMMs on channel; limiting to DDR3-1066\n");
+				}
+			} else {
+				/* Limit to DDR3-1333 */
+				if (freq > 666) {
+					freq = 666;
+					print_tf(__func__, ": 1 registered DIMM on channel; limiting to DDR3-1333\n");
    			}
    		}
+		} else {
+			/* K10 BKDG Rev. 3.62 Table 33 */
+			/* Limit to DDR3-1333 */
+			if (freq > 666) {
+				freq = 666;
+				print_tf(__func__, ": unbuffered DIMMs on channel; limiting to DDR3-1333\n");
+			}
    	}
    }

@@ -120,6 +149,9 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
 //C32
 #elif CONFIG_CPU_SOCKET_TYPE == 0x14
 #include "../amdmct/mct_ddr3/mctardk5.c"
+//G34
+#elif CONFIG_CPU_SOCKET_TYPE == 0x15
+#include "../amdmct/mct_ddr3/mctardk5.c"
 #endif

#else  /* DDR2 */
@@ -207,6 +239,7 @@ static void raminit_amdmct(struct sys_info *sysinfo)
    printk(BIOS_DEBUG, "raminit_amdmct end:\n");
 }

+#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
 static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
 {
    if (!sysinfo)
@@ -245,3 +278,4 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
    }
 #endif
 }
+#endif
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index c00cf24..444adc5 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -322,7 +322,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
    }

/* Set limits if needed */
-	pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), pDCTstat->PresetmaxFreq);
+	pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), (ch1_registered || ch2_registered), pDCTstat->PresetmaxFreq);
 }

#ifdef UNUSED_CODE