Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55151 )
Change subject: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP ......................................................................
soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP
This is to enable S0ix device specific method _DSM ( UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in.
Alone with this change, one coreboot and two kernel changes are also required: https://review.coreboot.org/c/coreboot/+/55127 https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281
Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I87fa55e4003e789d55ddce11d1f76e9ca8b08f18 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55151/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0c472d9..2e6034b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_S0IX select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI