[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45759 )

Change subject: soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
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Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45759/3/src/soc/intel/alderlake/acp... 
File src/soc/intel/alderlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/45759/3/src/soc/intel/alderlake/acp... 
PS3, Line 235: 		if (tbtbar && tbten) {
> Should there also be a check here depending on whether or not each device (00:07.0 - 7. […]

Ack

https://review.coreboot.org/c/coreboot/+/45759/7/src/soc/intel/alderlake/fsp... 
File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/45759/7/src/soc/intel/alderlake/fsp... 
PS7, Line 216: 		if (config->SataPortsEnableDitoConfig[i]) {
> suspect code indent for conditional statements (16, 32)

done