[coreboot-gerrit] Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47980 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

lp4x: Add new memory parts and generate SPDs

Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.

Add new generic SPD lp4x-spd-6.hex based on attributes of
MT53D512M64D4NW-046 WT:F.

BUG=b:172993397
TEST=none

Change-Id: I09c6eab640c169dbdb451964967d14a31e314496
Signed-off-by: Nick Vaccaro 
---
A src/soc/intel/tigerlake/spd/lp4x-spd-6.hex
M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
3 files changed, 46 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47980/1

diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex
new file mode 100644
index 0000000..f330d4b
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 00 08 00 00 00 00 02 01 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
[phone] 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
index c7e9690..3450f1f 100644
--- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
@@ -16,3 +16,4 @@
 H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex
 H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex
 MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex
+MT53D512M64D4NW-046 WT:F,lp4x-spd-6.hex
diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index 91062d0..7dc502e 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -217,6 +217,18 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
-        }
+        },
+	{
+            "name": "MT53D512M64D4NW-046 WT:F",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 1,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+	}
     ]
 }