[coreboot-gerrit] Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 )

Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support
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Patch Set 11:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... 
PS9, Line 84: 		mem_cfg->SpdAddressTable[0] = 0x0;
> I believe this UPD already defaults to 0. […]

Ack

https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... 
PS9, Line 84: 	mem_cfg->SpdAddressTable[0] = 0x0;
            : 		mem_cfg->SpdAddressTable[1] = 0x0;
            : 		mem_cfg->SpdAddressTable[2] = 0x0;
            : 		mem_cfg->SpdAddressTable[3] = 0x0;
> Based on the comment in the Fspm header file we are setting it to 0 when MemorySpdPtr is used.

Done

https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

PS5:
> Done

Done