Hello Richard Spiegel, Martin Roth, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32661
to review the following change.
Change subject: soc/amd/stoneyridge: Move sata to common ......................................................................
soc/amd/stoneyridge: Move sata to common
Relocate generic sata support from stoneyridge to common/block.
Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- A src/soc/amd/common/block/include/amdblocks/sata.h A src/soc/amd/common/block/sata/Kconfig A src/soc/amd/common/block/sata/Makefile.inc A src/soc/amd/common/block/sata/sata.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/sata.c 6 files changed, 83 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32661/1
diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h new file mode 100644 index 0000000..0469e7b --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_SATA_H__ +#define __STON__AMDBLOCKS_SATA_H__EYRIDGE_CPU_H__ + +#include <device/device.h> + +void soc_enable_sata_features(struct device *dev); + +#endif /* __AMDBLOCKS_SATA_H__ */ diff --git a/src/soc/amd/common/block/sata/Kconfig b/src/soc/amd/common/block/sata/Kconfig new file mode 100644 index 0000000..0c3d5bc --- /dev/null +++ b/src/soc/amd/common/block/sata/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SATA + bool + default n + help + Select this option to use AMD common SATA driver support. diff --git a/src/soc/amd/common/block/sata/Makefile.inc b/src/soc/amd/common/block/sata/Makefile.inc new file mode 100644 index 0000000..59b99eb --- /dev/null +++ b/src/soc/amd/common/block/sata/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += sata.c diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c new file mode 100644 index 0000000..905c145 --- /dev/null +++ b/src/soc/amd/common/block/sata/sata.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <amdblocks/sata.h> + +void __weak soc_enable_sata_features(struct device *dev) { } + +static void sata_init(struct device *dev) +{ + soc_enable_sata_features(dev); +} + +static struct pci_operations lops_pci = { + /* .set_subsystem = pci_dev_set_subsystem, */ +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .ops_pci = &lops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_CZ_SATA, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + 0 +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index cbb8ba0..a307f66 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -52,6 +52,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index f0dabe0..6740698 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -18,9 +18,10 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <amdblocks/sata.h> #include <soc/southbridge.h>
-static void soc_enable_sata_features(struct device *dev) +void soc_enable_sata_features(struct device *dev) { u8 *ahci_ptr; u32 misc_ctl, cap_cfg; @@ -45,32 +46,3 @@ temp &= ~SATA_MISC_SUBCLASS_WREN; pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); }; - -static void sata_init(struct device *dev) -{ - soc_enable_sata_features(dev); -} - -static struct pci_operations lops_pci = { - /* .set_subsystem = pci_dev_set_subsystem, */ -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .ops_pci = &lops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_CZ_SATA, - PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, - 0 -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, -};