[coreboot-gerrit] Patch merged into coreboot/master: amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability

the following patch was just integrated into master:
commit 45ded7df0317d2c898ed68e308f63d569e545658
Author: Timothy Pearson 
Date:   Thu Jun 4 00:10:03 2015 -0500

amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability

Upon bootup the hardware reads at minimum 256 * 16 bytes (4Kb, or 32KB) over
    I2C on a system with all DIMM slots populated.  If even one of those reads
    has a single flipped bit in it (due to EMI, cross coupling with another trace,
     or just poor margins on some cheap DIMM) the system will hang and require a
    hard reset.  In practice I've seen failure rates as high as 1 failed boot in
    50 due to this issue, granted with cheap DIMMs, but even so retrying the read
    resolves the corruption issue.

I2C is not designed for continuous data transmission with high reliability, and
    there is no hardware error checking, therefore a single retry when transferring
    this amount of data makes sense.

Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09
    Signed-off-by: Timothy Pearson 
    Reviewed-on: http://review.coreboot.org/11975
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi

See http://review.coreboot.org/11975 for details.

-gerrit