[coreboot-gerrit] Change in coreboot[master]: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits

[Angel Pons (Code Review)]

Hello  Felix Singer, build bot (Jenkins), Nico Huber, Arthur Heymans, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47038

to look at the new patch set (#3).

Change subject: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits
......................................................................

sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits

For all these southbridges, the lower nibble of PCICMD is read-only.

Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change.

Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/lpc.c
7 files changed, 0 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47038/3