Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Patrick Georgi, Martin Roth, Rizwan Qureshi, Krishna P Bhat D, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46312
to look at the new patch set (#6).
Change subject: soc/intel/common: Boot time optimization ......................................................................
soc/intel/common: Boot time optimization
CSE RW blob which will be used by coreboot to update CSE's RW partition, is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot time by around 300ms.
The patch address the boot time by pulling CSE RW blob outside of FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions(FW_MAIN_A_EXTN and FW_MAIN_B_EXTN) as a CBFS file.
The driver provides Kconfig options to place CSE RW blob into FW_MAIN_X or FW_MAIN_X_EXTN. These config options are CONFG_SOC_INTEL_CSE_LITE_SKU_1_0 and CONFIG_SOC_INTEL_CSE_LITE_SKU_2_0.
Chose Kconfig: CONFIG_SOC_INTEL_CSE_LITE_SKU_1_0 : To place CSE RW blob into FW_MAIN_A and FW_MAIN_B. CONFIG_SOC_INTEL_CSE_LITE_SKU_2_0 : To place CSE RW blob into FW_MAIN_A_EXTN and FW_MAIN_B_EXTN.
Boot Time Measurement details with CONFIG_SOC_INTEL_CSE_LITE_SKU_2_0: -------------------------------------------------------- | Platform | Old Boot Time | New Boot Time | -------------------------------------------------------- | JSL | 1.3s | 1.06s | -------------------------------------------------------- | TGL | 1.63s | 1.36s | --------------------------------------------------------
Changes: 1. Makefile changes to accommodate CSE RW blob part of FW_MAIN_A_EXTN/ FW_MAIN_B_EXTN and add RW blob metadata file part of FW_MAIN_A/B. 2. Kconfig change to define CBFS name and default file name for RW blob metadata. 3. CSE Lite Driver
BUG=b:169077783 TEST=Verified on hatch, JSL & TGL platforms
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 141 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46312/6