Jonathan A. Kollasch (jakllsch@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10983
-gerrit
commit 597fa2d582eda5f8dde4037d5beda4137ca7dc8b Author: Jonathan A. Kollasch jakllsch@kollasch.net Date: Mon Jul 20 07:43:32 2015 -0500
amdfam10/northbridge: fix amdfam10_scan_chain()
Fixes two issues introduced recently:
- The subordinate bus limit was reduced from essentially unlimited (0xfc) to 0 additional busses. This caused config space of subordinate busses of a non-primary HT IO chain to become unrouted (and thus invisible) during initial scan.
- The HTcap+0x14 register is *not* the same on K8 and 10h. 10h has isochronous HT link buffer controls where K8 had bus numbers.
These two issues resulted in the non-primary IO chain not having resources allocated to subordinate busses due to the devices being invisible during initial scan, and for MMIO accesses to devices on the base bus of the non-primary chain to stall the whole machine, presumably due to invalid HT buffer allocations.
Change-Id: I7a1f51bd91ab3dae6ed1c447209b36003830f3dc Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net --- src/northbridge/amd/amdfam10/northbridge.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f6f2641..7a0109e 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -142,7 +142,6 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) }
typedef enum { - HT_ROUTE_CLOSE, HT_ROUTE_SCAN, HT_ROUTE_FINAL, } scan_state; @@ -166,17 +165,8 @@ static void ht_route_link(struct bus *link, scan_state mode) * not correctly configured */ busses = pci_read_config32(link->dev, link->cap + 0x14); - busses &= 0xff000000; - busses |= parent->secondary & 0xff; - if (mode == HT_ROUTE_CLOSE) { - busses |= 0xfeff << 8; - } else if (mode == HT_ROUTE_SCAN) { - busses |= ((u32) link->secondary & 0xff) << 8; - busses |= 0xfc << 16; - } else if (mode == HT_ROUTE_FINAL) { - busses |= ((u32) link->secondary & 0xff) << 8; - busses |= ((u32) link->subordinate & 0xff) << 16; - } + busses &= 0xffff00ff; + busses |= ((u32) link->secondary & 0xff) << 8; pci_write_config32(link->dev, link->cap + 0x14, busses);
if (mode == HT_ROUTE_FINAL) { @@ -190,6 +180,7 @@ static void ht_route_link(struct bus *link, scan_state mode) static void amdfam10_scan_chain(struct bus *link) { unsigned int next_unitid; + uint16_t sub;
/* See if there is an available configuration space mapping * register in function 1. @@ -205,7 +196,10 @@ static void amdfam10_scan_chain(struct bus *link) ht_route_link(link, HT_ROUTE_SCAN);
/* set the config map space */ + sub = link->subordinate; + link->subordinate = 0xfc; set_config_map_reg(link); + link->subordinate = sub;
/* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link