Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35233 )
Change subject: intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/c/coreboot/+/35233/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35233/3//COMMIT_MSG@16 PS3, Line 16:
Could you please add the following? […]
Done
https://review.coreboot.org/c/coreboot/+/35233/3/src/drivers/intel/fsp2_0/Kc... File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/35233/3/src/drivers/intel/fsp2_0/Kc... PS3, Line 157: 0x10000
Did we establish that this size is valid for all platforms using 2.1? i.e. […]
Cleanest would be to explicitly have only SoC set the value. I would leave it to Intel to move this and sync it with their integration guides once they reach agreement:
CB:35233 Sep 03 07:36 Nathaniel comments 0x20000 for Cometlake, more for Copperlake.
CB:35165 Sep 03 09:05 Subrata comments 0x11000 for Cometlake, but decides to use 0x10000 instead.
https://review.coreboot.org/c/coreboot/+/35233/1/src/drivers/intel/fsp2_0/me... File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/35233/1/src/drivers/intel/fsp2_0/me... PS1, Line 37: 0x20000
I think it would be best to have a config option that can be provided by SoC to determine the size o […]
Done
https://review.coreboot.org/c/coreboot/+/35233/1/src/drivers/intel/fsp2_0/me... PS1, Line 37: 0x20000
Agreed with Furquan. We shouldn't hard-code this to 128KB. […]
Done
https://review.coreboot.org/c/coreboot/+/35233/1/src/soc/intel/cannonlake/Kc... File src/soc/intel/cannonlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/35233/1/src/soc/intel/cannonlake/Kc... PS1, Line 122: 0x20000
I believe we would still need a larger stack with FSP_USES_CB_STACK. […]
Done