Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )
Change subject: soc/intel/skylake: Drop redundant PcieRpEnable ......................................................................
soc/intel/skylake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead.
Note: Jenkins will fail because somebody has to go through all the dts.
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h A src/soc/intel/skylake/include/soc/pcie.h A src/soc/intel/skylake/pcie_rp.c M src/soc/intel/skylake/romstage/fsp_params.c 10 files changed, 53 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/79917/1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b580e76..684c131 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -7,37 +7,31 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enable PCIE slot - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1"
- register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2"
- register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3"
- register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4"
- register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5"
- register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 # RP17, uses CLK SRC 7 @@ -112,6 +106,12 @@ device ref i2c3 off end device ref sata on end device ref i2c4 off end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp14 on end + device ref pcie_rp17 on end device ref emmc off end device ref sdxc off end device ref hda on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b7c4395..ac384d7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -38,21 +38,18 @@
# Enable Root ports. # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2"
# PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3"
# PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" # RP6, uses CLK SRC 1 @@ -61,14 +58,12 @@ # PCIE Port 7 Disabled # PCIE Port 8 Disabled # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5"
# PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" # RP10, uses CLK SRC 4 diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index c5b7e94..18fe14e 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -81,13 +81,6 @@ .voltage_limit = 0 }"
- # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqSupport[3]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 2291c63..cb69194 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -77,12 +77,6 @@ .voltage_limit = 0 }"
- # Enable Root port. - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[16]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqSupport[4]" = "1" @@ -168,6 +162,7 @@ device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp5 on end + device ref pcie_rp17 on end device ref emmc off end device ref sdxc off end device ref lpc_espi on diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 732a98a..5da767b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += me.c +romstage-y += pcie_rp.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -50,6 +51,7 @@ ramstage-y += lpc.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-y += reset.c diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8df1ad3..f700c48 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -25,6 +25,7 @@ #include <soc/irq.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/usb.h> @@ -33,22 +34,6 @@
#include "chip.h"
-static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, - { 0 } -}; - -static const struct pcie_rp_group pch_h_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, - /* Sunrise Point PCH-H actually only has 4 ports in the - third group. But that would require a runtime check - and probing 4 non-existent ports shouldn't hurt. */ - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -180,10 +165,7 @@ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* swap enabled PCI ports in device tree if needed */ - if (CONFIG(SKYLAKE_SOC_PCH_H)) - pcie_rp_update_devicetree(pch_h_rp_groups); - else - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); }
struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 3070c46..7d928b5 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -172,13 +172,6 @@ } Peg2MaxLinkWidth;
/* - * Enable/Disable Root Port - * 0: Disable Root Port - * 1: Enable Root Port - */ - bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - - /* * Enable/Disable Clk-req support for Root Port * 0: Disable Clk-Req * 1: Enable Clk-req diff --git a/src/soc/intel/skylake/include/soc/pcie.h b/src/soc/intel/skylake/include/soc/pcie.h new file mode 100644 index 0000000..4c07131 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SKYLAKE_PCIE_H__ +#define __SOC_SKYLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); + +#endif /* __SOC_SKYLAKE_PCIE_H__ */ diff --git a/src/soc/intel/skylake/pcie_rp.c b/src/soc/intel/skylake/pcie_rp.c new file mode 100644 index 0000000..08e9c30 --- /dev/null +++ b/src/soc/intel/skylake/pcie_rp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + /* Sunrise Point PCH-H actually only has 4 ports in the + third group. But that would require a runtime check + and probing 4 non-existent ports shouldn't hurt. */ + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + if (CONFIG(SKYLAKE_SOC_PCH_H)) + return pch_h_rp_groups; + + return pch_lp_rp_groups; +} diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f24054a..ea68d94 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -4,10 +4,12 @@ #include <cpu/x86/msr.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <option.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h>
@@ -74,9 +76,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { - int i; - uint32_t mask = 0; - m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -91,11 +90,7 @@ m_cfg->DdrFreqLimit = 0; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->PrmrrSize = get_valid_prmrr_size(); - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1<<i); - } - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
cpu_flex_override(m_cfg);