Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47238
to look at the new patch set (#2).
Change subject: device/pciexp: Allow ASPM on bridge devices ......................................................................
device/pciexp: Allow ASPM on bridge devices
The device acceptable latency field is only valid for 'endpoints', but not for bridge devices. Set the maximum acceptable latency on such devices to allow ASPM being enabled if supported on both sides.
Allows the PCIe link on bridge devices to go into L0s/L1.
This allows the package to enter a deeper sleep state when all links are idle.
WARNING: This might cause issues on PCIe bridge devices that doesn't properly support ASPM. In addition it might decrease performance.
Change-Id: I277efe0bd1448ee8bff633428aa729aeedf04e28 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/device/pciexp_device.c 1 file changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47238/2