Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13405
-gerrit
commit 584ab43e9d8664fb1443934ce6ce973b12f9bb5f Author: Bora Guvendik bora.guvendik@intel.com Date: Thu Jan 14 13:19:37 2016 -0800
mainboard/apollolake: update flashmap offset for new master image
The new master image has new fmap offset
Change-Id: Ifd33a128979da783f978a86fced83c5f4d1dacc0 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- src/mainboard/intel/apollolake_rvp/Kconfig | 15 ++++++++++++--- src/mainboard/intel/apollolake_rvp/aplk.rvp.dts | 23 +++++++++++++++++++++++ 2 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index ec71e96..072ca49 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES + select USE_BLOBS
config MAINBOARD_DIR string @@ -18,9 +19,18 @@ config MAINBOARD_VENDOR string default "Intel"
+config FMAP_FILE + string + default aplk.rvp + +config PREBUILT_SPI_IMAGE + string + default aplk.rvp1.bin.orig if BOARD_INTEL_APOLLOLAKE_RVP1 + default aplk.rvp2.bin.orig if BOARD_INTEL_APOLLOLAKE_RVP2 + config IFD_BIOS_END hex - default 0x700000 + default 0x6FF000
config IFD_BIOS_START hex @@ -28,7 +38,6 @@ config IFD_BIOS_START
config FLASHMAP_OFFSET hex - default 0x3a3040 if BOARD_INTEL_APOLLOLAKE_RVP1 - default 0x3f10c0 if BOARD_INTEL_APOLLOLAKE_RVP2 + default 0x7e480
endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/aplk.rvp.dts b/src/mainboard/intel/apollolake_rvp/aplk.rvp.dts new file mode 100644 index 0000000..45f5dad --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/aplk.rvp.dts @@ -0,0 +1,23 @@ +firmware 8M { + + SI_HDR@0x0 4K { + SI_DESC 4K + } + + # IBBL is a 32 kb code block that is initially loaded by CSE firmware and + # is placed in shared SRAM. That SRAM area is mapped in 4G-32K area of + # the host CPU. Reset vector is set as usual. + IBBL @ 0x76480 32K + FMAP @ 0x7e480 2K + RW_SECTION_A @ 0x382000 { + VBLOCK_A 64K + FW_MAIN_A 768K + } + RW_SECTION_B @ 0x452000 { + VBLOCK_B 64K + FW_MAIN_B 768K + } + COREBOOT(CBFS) @ 0x522000 1456K + GBB @ 0x68e000 320K + } +