[coreboot-gerrit] Change in coreboot[master]: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default

[Michael Niewöhner (Code Review)]

Hello Patrick Rudolph, Angel Pons, Maxim Polyakov, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35745

to look at the new patch set (#3).

Change subject: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default
......................................................................

soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default

PCIe Advanced Error Reporting (AER) povides better error reporting for
PCIe devices/buses. This is enabled on most modern machines, so we
should do the same and enable it by default.

Tested on X11SSM-F

Signed-off-by: Michael Niewöhner 
Change-Id: I172329d8d42c3be02e64300675d646edfbee8b72
---
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/soc/intel/skylake/chip.c
11 files changed, 4 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35745/3