Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31444 )
Change subject: soc/intel/cannonlake: Add ASL function for setting pad mode ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31444/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31444/2//COMMIT_MSG@9 PS2, Line 9: funtion function
https://review.coreboot.org/#/c/31444/2/src/soc/intel/cannonlake/acpi/gpio_o... File src/soc/intel/cannonlake/acpi/gpio_op.asl:
https://review.coreboot.org/#/c/31444/2/src/soc/intel/cannonlake/acpi/gpio_o... PS2, Line 91: PADM, 2, IIRC, in the past we have had problems accessing individual bit fields in 32-bit regs. Instead we have used RMW operations to ensure there are no side-effects. Probably, we should be doing the same here?