Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74520 )
Change subject: mb/starlabs/starbook: Let coreboot configure ASPM ......................................................................
mb/starlabs/starbook: Let coreboot configure ASPM
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205) but coreboot's configuration results in lower power consumption of approximately 0.5W when idling - the reason why is unknown.
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520 Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb 2 files changed, 18 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 5ad7e27..b49a86d 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -147,30 +147,9 @@ string default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
-config PCIEXP_ASPM - bool - default n - help - FSP is already taking care of ASPM, which is configured through the devicetree in coreboot - on Alderlake Platforms. Disable it to save some boot time. - config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS default 32
-config PCIEXP_L1_SUB_STATE - bool - default n - help - Enabling PCIe L1 sub states is already done in FSP. - Disable it to save some boot time. - -config PCIEXP_CLK_PM - bool - default n - help - Enabling PCIe clock power management is already done in FSP. - Disable it to save some boot time - config SOC_INTEL_CSE_SEND_EOP_EARLY default n if BOARD_STARLABS_STARBOOK_ADL
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 5c54f4d..298ec19 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -100,8 +100,6 @@ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" @@ -119,8 +117,6 @@ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1,
}" smbios_slot_desc "SlotTypeM2Socket3"