[coreboot-gerrit] Change in coreboot[master]: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()

[Patrick Rudolph (Code Review)]

Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48658

to look at the new patch set (#2).

Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
......................................................................

soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()

The TPM memory MMIO range is always decoded by the PCH, regardless
if it's LPC, SPI or fTPM.

Add the memory range to fixed MMIO ranges list to prevent LGMR register
being written with this address. Reserved 32 KiB as that seems to be the
minimal common reserved size for the TPM MMIO area.

Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/alderlake/espi.c
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/elkhartlake/espi.c
M src/soc/intel/icelake/espi.c
M src/soc/intel/jasperlake/espi.c
M src/soc/intel/skylake/lpc.c
M src/soc/intel/tigerlake/espi.c
M src/soc/intel/xeon_sp/lpc.c
9 files changed, 18 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/2