Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44049 )
Change subject: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 ......................................................................
Patch Set 1: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/44049/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44049/1//COMMIT_MSG@9 PS1, Line 9: of remove 'of'
https://review.coreboot.org/c/coreboot/+/44049/1//COMMIT_MSG@13 PS1, Line 13: implmentation impl*e*mentation
https://review.coreboot.org/c/coreboot/+/44049/1//COMMIT_MSG@17 PS1, Line 17: DCACHE_RAM_SIZE Put on the next line
https://review.coreboot.org/c/coreboot/+/44049/1/src/soc/intel/xeon_sp/cpx/K... File src/soc/intel/xeon_sp/cpx/Kconfig:
https://review.coreboot.org/c/coreboot/+/44049/1/src/soc/intel/xeon_sp/cpx/K... PS1, Line 9: select PLATFORM_USES_FSP2_2 This should be selected from `config SOC_INTEL_COOPERLAKE_SP`