Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email )
Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80795/comment/1b31cc7c_1597d468 : PS1, Line 10: hidden the fast_spi driver will generate the _CRS marking the BAR
Usually only the VENDOR/DEVID changes to 0xffffffff when a device is hidden. […]
I see. I suppose if fast_spi is hidden, fast_spi driver will not be called at all, and no CRS will be reported. However, my platform is with fast_spi unhidden hence I cannot test to prove.
In an unhidden platform, fast_spi's BAR will be relocated by coreboot's resource allocator in low MMIO space as a normal allocation and the uncore _CRS reporting is not needed. Hence I agree on this patch but suggest to update the commit message to fit for the unhidden case.
P.S. pci 0000:00:1f.5: reg 0x10: [mem 0x955fd000-0x955fdfff] pci 0000:00:1f.5: reg 0x14: [mem 0x92000000-0x93ffffff]
For the hidden case, we can make additional fix if there is a platform with that configuration is used.
Your opinion?