Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29072
Change subject: soc/amd/stoneyridge: Rearrange southbridge.h more ......................................................................
soc/amd/stoneyridge: Rearrange southbridge.h more
Move the SPI base address register definition to D14F3. This was missed in: bba043 amd/stoneyridge: Rearrange southbridge.h
Change-Id: Ia722339418c118bdf4b000bbf97ae4266e9b3be2 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29072/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 896d494..403e980 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -102,13 +102,6 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0)
-#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ABORT_ENABLE BIT(2) -#define SPI_ROM_ENABLE BIT(1) -#define SPI_ROM_ALT_ENABLE BIT(0) -#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK2_REQ_MAP_SHIFT 8 @@ -310,6 +303,13 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90
+#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + /* LPC register 0xb8 is DWORD, here there are definitions for byte access. For example, bits 31-24 are accessed through byte access at register 0xbb. */