[coreboot-gerrit] Change in ...coreboot[master]: drivers/intel/fsp1_1: Print the MTRR's FSP-T set up

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30876 )

Change subject: drivers/intel/fsp1_1: Print the MTRR's FSP-T set up
......................................................................

drivers/intel/fsp1_1: Print the MTRR's FSP-T set up

Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/30876
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Kyösti Mälkki 
---
M src/drivers/intel/fsp1_1/car.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 79dd368..3a41e40 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -64,6 +64,8 @@
    printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
    printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);

+	display_mtrrs();
+
    if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
        car_params->bootloader_car_end !=
    		(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {