[coreboot-gerrit] Change in coreboot[master]: HACK: soc/mediatek: Add function to raise the big CPU frequency

[Yidi Lin (Code Review)]

Hello Weiyi Lu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46410

to review the following change.

Change subject: HACK: soc/mediatek: Add function to raise the big CPU frequency
......................................................................

HACK: soc/mediatek: Add function to raise the big CPU frequency

Implement mt_pll_raise_ca76_freq() in MT8192 to raise the frequency.
usage: mt_pll_raise_ca76_freq(2200UL * MHz);

Signed-off-by: Weiyi Lu 
Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46410/1

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index d9ba230..54b12e8 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -59,6 +59,7 @@
 int pll_set_rate(const struct pll *pll, u32 rate);
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
+void mt_pll_raise_ca76_freq(u32 freq);

enum fmeter_type {
    FMETER_ABIST = 0,
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 0366cd6..cd65d25 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -546,3 +546,30 @@

return 0;
 }
+
+void mt_pll_raise_ca76_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch ca76 clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK,
+		MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable armpll_bl frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN);
+
+	/* raise armpll_bl frequency */
+	pll_set_rate(&plls[APMIXED_ARMPLL_BL], freq);
+
+	/* enable armpll_bl frequency output */
+	setbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch ca76 clock source back to armpll_bl */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK,
+		MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}