[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48619 )

Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
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mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports

This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.
Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543

Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51
Signed-off-by: V Sowmya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index b6d3ff3..369ce21 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -15,6 +15,7 @@
    select SOC_INTEL_ALDERLAKE
    select HAVE_SPD_IN_CBFS
    select DRIVERS_SOUNDWIRE_ALC711
+	select PCIEXP_HOTPLUG

config CHROMEOS
    bool
@@ -77,6 +78,18 @@
    select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
 endchoice

+config PCIEXP_HOTPLUG_BUSES
+	int
+	default 42
+
+config PCIEXP_HOTPLUG_MEM
+	hex
+	default 0xc200000  # 194 MiB
+
+config PCIEXP_HOTPLUG_PREFETCH_MEM
+	hex
+	default 0x1c000000 # 448 MiB
+
 config VBOOT
    select VBOOT_LID_SWITCH
    select VBOOT_MOCK_SECDATA