[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59363 )

Change subject: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake
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soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake

TEST=Verified on Brya

Signed-off-by: Sridahr Siricilla 
Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59363/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 58b9051..1f02046 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -46,6 +46,7 @@
    select SOC_INTEL_COMMON_BLOCK
    select SOC_INTEL_COMMON_BLOCK_ACPI
    select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
+	select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
    select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
    select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
    select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ