Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34337 )
Change subject: soc/intel/common: add advanced macros for gpio config ......................................................................
soc/intel/common: add advanced macros for gpio config
In the case there is no the circuit diagram for motherboard, the PCH/SoC GPIOs config is based on information from the inteltool dump. However, available macros from gpio_defs.h can't define the pad configuration from this dump. This patch resolve this problem by adding advanced macros:
PAD_CFG_ADV_NF(pad, pull, rst, bufdis, trig, func), PAD_CFG_ADV_GPO(pad, val, pull, trig, rst)
Unlike PAD_CFG_NF and PAD_CFG_GPO, these new macros allow to set: trig - RX Level/Edge Configuration, RXEVCFG field in DW0 reg[1] bufdis - GPIORXDIS/GPIOTXDIS fields in DW0 to disable the input/ output buffer[1] of pad (PAD_CFG_ADV_NF only)
These changes were tested on Asrock H110M-DVS motherboard[2]. It also resolves the problem of automatically creating pads configuration[3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/33565 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/34337/1
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index bdbc323..ff9781b 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -43,3 +43,11 @@ depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n + +# Indicate if SoC supports advanced macros of GPIOs. Unlike the standard ones, +# these macros have an increased number of parameters for configuring the pad. +config SOC_INTEL_COMMON_BLOCK_GPIO_ADVANCED_MACROS + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool + default n + diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index e1ddd4b..8b3daf6 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -409,4 +409,26 @@
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ADVANCED_MACROS) + +/* Disable the input or output buffer of the pad */ +#define PAD_CFG0_BUF_RX_DIS PAD_CFG0_RX_DISABLE +#define PAD_CFG0_BUF_TX_DIS PAD_CFG0_TX_DISABLE +#define PAD_CFG0_BUF_BOTH_DIS PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE +#define PAD_CFG0_BUF_EN 0 + +/* Advanced function configuration */ +#define PAD_CFG_ADV_NF(pad, pull, rst, bufdis, trig, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_BUF_##bufdis | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + +/* Advanced settings for general purpose output */ +#define PAD_CFG_ADV_GPO(pad, val, pull, rst, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ADVANCED_MACROS */ + #endif /* _SOC_BLOCK_GPIO_DEFS_H_ */