[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE

[Subrata Banik (Code Review)]

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik.

Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85025?usp=email )

Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE
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Patch Set 2:

(1 comment)

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/85025/comment/a6a818c4_f49498fb?usp... :
PS1, Line 496: pmc_enable_pm1_control(pm1_cnt_value)
> Acknowledged

i guess with line 492, we can safely assume that all SLP_TYPE offsets are cleared otherwise, we won't be landing inside this `if` loop. I'm  avoiding steps to clear the slp_type and reading the pm1_cnt that i have introduced with my last patchset.