[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios

[Vinay Kumar (Code Review)]

Attention is currently required from: V Sowmya.
Vinay Kumar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54055 )

Change subject: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios
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Patch Set 4:

(1 comment)

This change is ready for review.

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/54055/comment/f17900fd_5e056497 
PS4, Line 329: 	params->PchFivrExtVnnRailSxEnabledStates = 0x3f;
For Brya board, PchFivrExtV1p05RailEnabledStates, PchFivrExtVnnRailEnabledStates and PchFivrExtVnnRailSxEnabledStates should be set to 0x0(disabled). This is because Brya does not have VNN and V1P05 external bypass rails implemented. Other voltage and Iccmax settings for ExtV1p05/Vnn rails are not required for Brya board.