30 Aug
2019
30 Aug
'19
8:14 p.m.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35161 )
Change subject: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35161/1/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/35161/1/src/arch/x86/postcar_loader... PS1, Line 129:
Seems PARALLEL_MP init sets final MTRRs for BSP before memcpy() of smmstub. […]
Sounds good. Thanks for the confirmation, Kyösti.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Gerrit-Change-Number: 35161
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Kane Chen kane.chen@intel.com
Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Shelley Chen shchen@google.com
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
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Gerrit-Comment-Date: Fri, 30 Aug 2019 18:14:33 +0000
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