Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48632 )
Change subject: soc/amd/picasso: Fix ACPI PCI routing table
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48632/4/src/soc/amd/picasso/pcie_gp...
File src/soc/amd/picasso/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/48632/4/src/soc/amd/picasso/pcie_gp...
PS4, Line 106: 0x0000FFFF
shouldn't this rather be: […]
It's 0x0000FFFF because there is only one device on each bridge:
-[0000:00]-+-00.0
+-00.2
+-01.0
+-01.2-[01]----00.0 <-- 00.X
+-01.3-[02]----00.0 <-- 00.X
+-08.0
+-08.1-[03]--+-00.0 <-- 00.X
| +-00.1
| +-00.2
| +-00.3
| +-00.5
| -00.7
--
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Gerrit-Project: coreboot
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