Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35383 )
Change subject: drivers/intel/fsp2_0: Allow platform to increase mem overhead ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35383/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35383/1//COMMIT_MSG@13 PS1, Line 13: AMD TSEG
I was wondering if there were alignment requirements. […]
TSEG has its own typing, independent of the MTRRs, so I don't believe that should be an issue. And SMM typing gets first crack; the MTRRs don't need to be programmed around it. As far as the alignment is concerned, it just means we burn a little DRAM. But in ST we ALIGN_DOWN from TSEG/BERT 8MB to calculate cbmem_top. I think the math typically works out that we don't burn any memory there, however we were comfortable with up to 8MB (more actually, but let's not get too far into the weeds). If we allocate in cbmem instead, then the worst case scenario seems much better.
https://review.coreboot.org/c/coreboot/+/35383/1/src/drivers/intel/fsp2_0/me... File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/35383/1/src/drivers/intel/fsp2_0/me... PS1, Line 44: __weak size_t platform_mem_overhead_size(void) { return 0; }
I see that you are carving out the BERT and TSEG region from the upper end of memory below 4GiB. […]
Yep, that's what I was doing as a quick experiment.