[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Add board id for MR DDR5 SKU

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52760 )

Change subject: mb/intel/adlrvp: Add board id for MR DDR5 SKU
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mb/intel/adlrvp: Add board id for MR DDR5 SKU

Add support for Maple Ridge DDR5 SKU with boardid 0x16

TEST=Verified build for ADL-P Chrome RVP
Signed-off-by: Deepti Deshatty 
Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760
Tested-by: build bot (Jenkins) 
Reviewed-by: Meera Ravindranath 
Reviewed-by: Maulik V Vaghela 
Reviewed-by: V Sowmya 
---
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/mainboard.c
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
4 files changed, 8 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  V Sowmya: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved
  Meera Ravindranath: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index af64148..9a94db2 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -13,7 +13,8 @@
    ADL_P_LP4_1 = 0x10,
    ADL_P_LP4_2 = 0x11,
    /* ADL-P DDR5 RVPs */
-	ADL_P_DDR5 = 0x12,
+	ADL_P_DDR5_1 = 0x12,
+	ADL_P_DDR5_2 = 0x16,
    /* ADL-P LPDDR5 RVP */
    ADL_P_LP5_1 = 0x13,
    ADL_P_LP5_2 = 0x17,
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 0ab80d2..eb86773 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -47,7 +47,8 @@
    case ADL_P_LP5_1:
    case ADL_P_LP5_2:
    	return "vbt_adlrvp_lp5.bin";
-	case ADL_P_DDR5:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
    	return "vbt_adlrvp_ddr5.bin";
    default:
    	return "vbt.bin";
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 29eb744..353cf4e 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -300,7 +300,8 @@
    case ADL_P_DDR4_1:
    case ADL_P_DDR4_2:
    	return &ddr4_mem_config;
-	case ADL_P_DDR5:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
    	return &ddr5_mem_config;
    case ADL_P_LP5_1:
    case ADL_P_LP5_2:
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 2c61125..9fff257 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -52,7 +52,8 @@
    switch (board_id) {
    case ADL_P_DDR4_1:
    case ADL_P_DDR4_2:
-	case ADL_P_DDR5:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
    	memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated);
    	break;
    case ADL_P_LP4_1: