Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42790 )
Change subject: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry ......................................................................
Patch Set 5:
Patch Set 5: Code-Review-1
Is there a reason this can't go in soc/intel/tigerlake/me?
Ideally calling the sync in BS_DEV_INIT_CHIPS should have been common for all SoCs, and hence there was no choice provided to the SoC code to choose where the sync was called.
To address the the TGL anomaly we can 1. Add a SoC specific switch like this patch 2. Create couple Kconfig options, by which SoC can select which stage to call the sync One to specify the stage and the other for entry or exit Will require some plumbing to handle the stage and entry exit options 3. Or provide full freedom to SoC code to call this function wherever it wants this will require to make sure it calls the cse_fw_sync function apart from selecting the Kconfig SoC code is responsible for keeping in mind the valid scope/stage of calling this function
Any simpler approach Since this is a more of a workaround until we root cause and fix the issue, option 1 seems like a simpler one to choose. Tim, Let me know your thoughts