[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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Patch Set 2:

(2 comments)

File src/soc/intel/alderlake/xhci.c:

https://review.coreboot.org/c/coreboot/+/55230/comment/3de69ad7_3f82d954 
PS1, Line 18: 0x490
> @Tim, I'm working with our internal teams for doc update. sorry for the confusion.

Oh oops I had PCH on the brain, you're right, thanks.

https://review.coreboot.org/c/coreboot/+/55230/comment/c4548ba9_43682e14 
PS1, Line 19: 10
> This needs correction as well since ADL-P CPU doesn't support USB2 ports. […]

You're right, should be 0