[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code

[Jeff Daly (Code Review)]

Jeff Daly has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71611 )

Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
......................................................................

soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code

Use Intel common SoC XHCI code for Denverton refactor

Signed-off-by: Jeff Daly 
Change-Id: I24ecd6b1bd0bdf1c3c1e32978a9048a22b294b15
---
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/xhci.c
3 files changed, 29 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/71611/1

diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 9931fb6..3ae757e 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -148,6 +148,7 @@
    PCI_DID_INTEL_ADP_P_XHCI,
    PCI_DID_INTEL_ADP_S_XHCI,
    PCI_DID_INTEL_ADP_M_XHCI,
+	PCI_DID_INTEL_DNV_XHCI,
    0
 };

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index dcf9a5f..9e169bb 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -43,6 +43,7 @@
    select SOC_INTEL_COMMON_BLOCK_SMBUS
    select SUPPORT_CPU_UCODE_IN_CBFS
    select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select SOC_INTEL_COMMON_BLOCK_XHCI
    select TSC_MONOTONIC_TIMER
    select TSC_SYNC_MFENCE
    select UDELAY_TSC
diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c
index 2760120..30bb479 100644
--- a/src/soc/intel/denverton_ns/xhci.c
+++ b/src/soc/intel/denverton_ns/xhci.c
@@ -1,36 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
+#include <device/pci_type.h>
+#include <intelblocks/xhci.h>

-#include <soc/pci_devs.h>
-#include <soc/ramstage.h>
+#define XHCI_USB2_PORT_STATUS_REG	0x480
+#define XHCI_USB3_PORT_STATUS_REG	0x4C0
+#define XHCI_USB2_PORT_NUM		4
+#define XHCI_USB3_PORT_NUM		4

-static void usb_xhci_init(struct device *dev)
+static const struct xhci_usb_info usb_info = {
+	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
+
+const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
 {
-	/* USB XHCI configuration is handled by the FSP */
-
-	printk(BIOS_NOTICE, "pch: %s\n", __func__);
-
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+	return &usb_info;
 }
-
-static struct device_operations usb_xhci_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = usb_xhci_init,
-	.enable = pci_dev_enable_resources,
-	.ops_pci = &soc_pci_ops,
-};
-
-static const struct pci_driver pch_usb_xhci __pci_driver = {
-	.ops = &usb_xhci_ops,
-	.vendor = PCI_VID_INTEL,
-	.device = PCI_DID_INTEL_DNV_XHCI,
-};