Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33142
Change subject: Kconfig: Create coreboot separate stage kconfigs ......................................................................
Kconfig: Create coreboot separate stage kconfigs
This patch creates seperate stage configs as below 1. STAGE_BOOTBLOCK 2. STAGE_VERSTAGE 3. STAGE_ROMSTAGE 4. STAGE_RAMSTAGE
A stage can only be enabled if soc has selected its supported architecture(example: arm, ppc, riscv, x86)
Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/Kconfig 1 file changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33142/1
diff --git a/src/Kconfig b/src/Kconfig index d30aa99..4c1fe32 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -18,6 +18,38 @@
menu "General setup"
+config STAGE_BOOTBLOCK + bool "Enable bootblock stage" + default y if ARCH_BOOTBLOCK_PPC64 || ARCH_BOOTBLOCK_ARMV8_64 || ARCH_BOOTBLOCK_ARM64 || ARCH_BOOTBLOCK_ARMV7 || ARCH_BOOTBLOCK_ARMV7_M || ARCH_BOOTBLOCK_ARMV7_R || ARCH_BOOTBLOCK_ARM || ARCH_BOOTBLOCK_ARMV4 || ARCH_BOOTBLOCK_RISCV || ARCH_BOOTBLOCK_X86_32 || ARCH_BOOTBLOCK_X86_64 || ARCH_BOOTBLOCK_MIPS + default n + help + This option is enabled if soc has selected any of supported + bootblock architecture (example: arm, ppc, riscv, x86). + +config STAGE_VERSTAGE + bool "Enable verstage stage" + default y if ARCH_VERSTAGE_PPC64 || ARCH_VERSTAGE_ARMV8_64 || ARCH_VERSTAGE_ARM64 || ARCH_VERSTAGE_ARMV7 || ARCH_VERSTAGE_ARMV7_M || ARCH_VERSTAGE_ARMV7_R || ARCH_VERSTAGE_ARM || ARCH_VERSTAGE_ARMV4 || ARCH_VERSTAGE_RISCV || ARCH_VERSTAGE_X86_32 || ARCH_VERSTAGE_X86_64 || ARCH_VERSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + verstage architecture (example: arm, ppc, riscv, x86). + +config STAGE_ROMSTAGE + bool "Enable romstage stage" + default y if ARCH_ROMSTAGE_PPC64 || ARCH_ROMSTAGE_ARMV8_64 || ARCH_ROMSTAGE_ARM64 || ARCH_ROMSTAGE_ARMV7 || ARCH_ROMSTAGE_ARMV7_R || ARCH_ROMSTAGE_ARM || ARCH_ROMSTAGE_ARMV4 || ARCH_ROMSTAGE_RISCV || ARCH_ROMSTAGE_X86_32 || ARCH_ROMSTAGE_X86_64 || ARCH_ROMSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + romstage architecture (example: arm, ppc, riscv, x86). + +config STAGE_RAMSTAGE + bool "Enable ramstage stage" + default y if ARCH_RAMSTAGE_PPC64 || ARCH_RAMSTAGE_ARMV8_64 || ARCH_RAMSTAGE_ARM64 || ARCH_RAMSTAGE_ARMV7 || ARCH_RAMSTAGE_ARMV7_R || ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_ARMV4 || ARCH_RAMSTAGE_RISCV || ARCH_RAMSTAGE_X86_32 || ARCH_RAMSTAGE_X86_64 || ARCH_RAMSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + ramstage architecture (example: arm, ppc, riscv, x86). + config COREBOOT_BUILD bool default y