Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8d066f3..63bd881 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -84,11 +84,13 @@
config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x40400 if SOC_INTEL_TIGERLAKE + default 0x30400 if SOC_INTEL_JASPERLAKE help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage + stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE hex