[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede/var/metaknight: Update DPTF parameters

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54046 )

Change subject: mb/google/dedede/var/metaknight: Update DPTF parameters
......................................................................

mb/google/dedede/var/metaknight: Update DPTF parameters

Remove TSR2 and use DPTF parameters from internal thermal team.

BUG=b:175938681
TEST=build and boot to OS.

Signed-off-by: David Wu 
Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54046
Tested-by: build bot (Jenkins) 
Reviewed-by: Raymond Wong 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Evan Green 
Reviewed-by: Sumeet R Pawnikar 
---
M src/mainboard/google/dedede/variants/metaknight/overridetree.cb
1 file changed, 40 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sumeet R Pawnikar: Looks good to me, approved
  Evan Green: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved
  Raymond Wong: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index c8c56f9..d4c9eca 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -64,7 +64,47 @@
    	[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
    }"

+	register "power_limits_config" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 12,
+	}"
+
    device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""CPU""
+
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU, CPU,           90, 5000),
+					[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 6000),
+					[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000)}"
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,           105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,  90, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,  80, SHUTDOWN)}"
+				register "controls.power_limits.pl1" = "{
+					.min_power = 3000,
+					.max_power = 6000,
+					.time_window_min = 1 * MSECS_PER_SEC,
+					.time_window_max = 1 * MSECS_PER_SEC,
+					.granularity = 125,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 12000,
+					.max_power = 12000,
+					.time_window_min = 1 * MSECS_PER_SEC,
+					.time_window_max = 1 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 3000 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				device generic 0 on end
+			end
+		end # SA Thermal device
    	device pci 14.0 on
    		chip drivers/usb/acpi
    			device usb 0.0 on