[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Set xHCI LFPS period sampling off time

[Ben Kao (Code Review)]

Ben Kao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56063 )

Change subject: soc/intel/jasperlake: Set xHCI LFPS period sampling off time
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soc/intel/jasperlake: Set xHCI LFPS period sampling off time

Provide a option to set xHCI LFPS period sampling off time.
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.

BUG=b:187801363
TEST=build coreboot with XhciLfpsSamplingOffTime and flash the
image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Ben Kao 
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/finalize.c
3 files changed, 42 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/56063/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 9064297..ae4d5a3 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -206,6 +206,9 @@
    # Enable HECI
    register "HeciEnabled" = "1"

+	# Set xHCI LFPS period sampling off time, the default is 9.
+	register "XhciLfpsSamplingOffTime" = "9"
+
    device domain 0 on
    	device pci 00.0 on end # Host Bridge
    	device pci 02.0 on end # Integrated Graphics Device
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 36e9a13..cd71501 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -85,6 +85,11 @@
    /* Wake Enable Bitmap for USB3 ports */
    uint16_t usb3_wake_enable_bitmap;

+	/* Set the LFPS periodic sampling off time for USB3 Ports.
+	 * Default value of PMCTRL_REG bits[7:4] is 9 which means periodic
+	 * sampling off interval is 9ms, the range is from 0 to 15. */
+	uint8_t XhciLfpsSamplingOffTime;
+
    /* SATA related */
    uint8_t SataMode;
    uint8_t SataSalpSupport;
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index 8219f0c..0ff55ee 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -26,6 +26,11 @@
 #define MIPI_CLK		(1 << 0)
 #define HDPLL_CLK		(0 << 0)

+#define XHCI_PMCTRL			0x80A4
+/* BIT[7:4] LFPS periodic sampling off time for USB3 Ports */
+#define PMCTRL_LFPS_OFFTIME_OFFSET	4
+#define PMCTRL_LFPS_OFFTIME_MAX		0xF
+
 static void pch_enable_isclk(void)
 {
    pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
@@ -38,6 +43,32 @@
    	pch_enable_isclk();
 }

+static void set_xhci_lfps_sampling_offtime(uint8_t time_ms)
+{
+	void *addr;
+	uint32_t reg;
+	struct device *xhci_dev = PCH_DEV_XHCI;
+	const struct resource *res;
+
+	res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
+	if (!res)
+		return;
+
+	if (time_ms > PMCTRL_LFPS_OFFTIME_MAX)
+		time_ms = PMCTRL_LFPS_OFFTIME_MAX;
+
+	addr = (void *)(uintptr_t)(res->base + XHCI_PMCTRL);
+	reg = read32(addr);
+	if ((reg >> PMCTRL_LFPS_OFFTIME_OFFSET & PMCTRL_LFPS_OFFTIME_MAX) ==
+			time_ms)
+		return;
+
+	reg &= ~(PMCTRL_LFPS_OFFTIME_MAX << PMCTRL_LFPS_OFFTIME_OFFSET);
+	reg |= time_ms << PMCTRL_LFPS_OFFTIME_OFFSET;
+	write32(addr, reg);
+	printk(BIOS_DEBUG, "Set XHCI PMCTRL register value 0x%x\n", reg);
+}
+
 static void pch_finalize(void)
 {
    uint32_t reg32;
@@ -75,6 +106,9 @@
    	write32(pmcbase + CPPMVRIC3, reg32);
    }

+	/* Set xHCI LFPS period sampling off time */
+	set_xhci_lfps_sampling_offtime(config->XhciLfpsSamplingOffTime);
+
    pch_handle_sideband(config);

pmc_clear_pmcon_sts();