[coreboot-gerrit] Change in coreboot[master]: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL

[Shreesh Chhabbi (Code Review)]

Hello Shreesh Chhabbi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48286

to review the following change.

Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL
......................................................................

src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL

Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.

Bug=b:171601324
BRANCH=volteer
Test=[to be updated]

Signed-off-by: Shreesh Chhabbi 
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/tigerlake/Kconfig
3 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48286/1

diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 912760e..2b630d0 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -51,6 +51,14 @@
      ENHANCED NEM guarantees that modified data is always
      kept in cache while clean data is replaced.

+config CAR_HAS_SF_MASKS
+	bool
+	depends on INTEL_CAR_NEM_ENHANCED
+	help
+	  In the case of non-inclusive cache architecture Snoop Filter MSR
+	  IA32_L3_SF_MASK_x programming is required along with the data ways.
+	  This is applicable for TGL and beyond.
+
 config COS_MAPPED_TO_MSB
    bool
    depends on INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 7408822..93f5f95 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -414,6 +414,35 @@
 set_eviction_mask:
    mov	%ebx, %ecx /* back up the number of ways */
    mov	%eax, %ebx /* back up the non-eviction mask*/
+	mov	%ecx, %edi /* back up the number of ways */
+
+#if CONFIG(CAR_HAS_SF_MASKS)
+	/*
+	 * If total number of available ways is X, SF mask is ((0x1 << X*2) - 1)
+	 */
+	mov     $0x02, %eax
+	mul     %ecx
+	mov     %eax, %ecx
+	mov     $0x01, %eax
+	shl	%cl, %eax
+	subl    $0x01, %eax /* Holds the SF mask */
+	/*
+	 * Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with
+	 * total number of LLC ways
+	 */
+	movl	$IA32_CR_SF_QOS_MASK_1, %ecx
+	xorl	%edx, %edx
+	wrmsr
+	/*
+	 * Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with
+	 * total number of LLC ways
+	 */
+	movl	$IA32_CR_SF_QOS_MASK_2, %ecx
+	xorl	%edx, %edx
+	wrmsr
+	mov	%edi, %ecx /* Restore number of ways */
+#endif
+	
    /*
     * Program MSR 0xC91 IA32_L3_MASK_1
     * This MSR contain one bit per each way of LLC
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index f53c18a..dd14ad2 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -24,6 +24,7 @@
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
    select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
+	select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
    select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP