[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add VR config for CFL, CNL and WHL

[Jamie Chen (Code Review)]

Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37466 )

Change subject: soc/intel/cannonlake: Add VR config for CFL, CNL and WHL
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Patch Set 4:

1. Could you help to add CML data as below?
Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML.

*   Platform             Segment                  SA       IA      GT (GT/GTx)
     * -----------------------------------------------------------------------------
     *  CML-U v1/v2           (15W) GT2 hexa            6        85(70) 31
     *  CML-U v1/v2           (15W) GT2 quad            6        85(70) 31
     *  CML-U v1/v2           (15W) GT2 dual            6        35     31
     *  CML-H                 (65W) GT2 octa           11.1     192(165)32
     *  CML-H                 (45W) GT2 octa           11.1     165(140)32
     *  CML-H                 (45W) GT2 hexa           11.1     140(128)32
     *  CML-H                 (45W) GT2 quad           11.1     105(86) 32
     *  CML-S                 (125W)GT2 deca           11.1     245(210)35
     *  CML-S                 (125W)GT2 octa           11.1     245(210)35
     *  CML-S                 (125W)GT2 hexa           11.1     140     35
     *  CML-S XeonW           (80W) GT2 deca           11.1     210     35
     *  CML-S XeonW           (80W) GT2 octa           11.1     210     35
     *  CML-S XeonW           (80W) GT2 hexa           11.1     140     35
     *  CML-S                 (65W) GT2 deca           11.1     210(175)35 
     *  CML-S                 (65W) GT2 octa           11.1     210(175)35
     *  CML-S                 (65W) GT2 hexa           11.1     140     35
     *  CML-S                 (35W) GT2 deca           11.1     140(104)35
     *  CML-S                 (35W) GT2 octa           11.1     140(104)35
     *  CML-S                 (35W) GT2 hexa           11.1     104     35
    ()= if device use baseline VR design.
2. There are two kinds of VR design on CML PDG.(One is baseline, the other is performance)
Could you add a config for switching two kinds of value?
Ex: 
switch(mch_id) {
...
    case PCI_DEVICE_ID_INTEL_CML_ULT
    case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: {
#if CONFIG(VR_CONFIG_BASELINE)
    	uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31);
#else
    	uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31);
#endif

return icc_max[domain];
    }
    case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: {
    	uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31);

return icc_max[domain];
    }
    case PCI_DEVICE_ID_INTEL_CML_H_8_2: {
    	uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32);
    	if (tdp >= 54)
#if CONFIG(VR_CONFIG_BASELINE)
    		icc_max[VR_IA_CORE] = VR_CFG_AMP(165);
#else
    		icc_max[VR_IA_CORE] = VR_CFG_AMP(192);
#endif
    	else
#if CONFIG(VR_CONFIG_BASELINE)
    		icc_max[VR_IA_CORE] = VR_CFG_AMP(140);
#else
    		icc_max[VR_IA_CORE] = VR_CFG_AMP(165);
#endif
    }
...