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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57291
to look at the new patch set (#3).
Change subject: [WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup ......................................................................
[WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup
Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called.
Haven't probed any SCL signal on the non-SOC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/stoneyridge/bootblock.c 3 files changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/57291/3