[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param

[Johannes Hahn (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Johannes Hahn, Uwe Poeche, Werner Zeh.

Hello Intel coreboot Reviewers, Mario Scheithauer, Uwe Poeche, Werner Zeh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86068?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
......................................................................

soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param

According to Intel's recommendation for Time Coordinated Computing (TCC)
the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled'
in order to promote low latencies on the PCH.
With the previous setting 'Disbaled' low latencies on the PCH for
I/O operations are not enhanced.

Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5
Signed-off-by: Johannes Hahn 
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/86068/2