[coreboot-gerrit] Change in coreboot[master]: cpu/intel/xeonsp: Cache BIOS SPI region

[Andrey Petrov (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39050

to look at the new patch set (#2).

Change subject: cpu/intel/xeonsp: Cache BIOS SPI region
......................................................................

cpu/intel/xeonsp: Cache BIOS SPI region

Instead of trying to hardcode caching parameters for FSP-T, use common
code to cache BIOS region. This seems to be an undocumented requirement
for FSP-M to function correctly.

Change-Id: I926722ecd7237bea236a4906b899a51e4963f740
Signed-off-by: Andrey Petrov 
---
M src/cpu/intel/xeonsp/Kconfig
M src/cpu/intel/xeonsp/Makefile.inc
M src/cpu/intel/xeonsp/bootblock.c
A src/cpu/intel/xeonsp/spi.c
4 files changed, 32 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/39050/2