[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39710 )

Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
......................................................................

soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN

BUG=b:151161585
BRANCH=none
TEST=build and boot ripto/volteer and check FSP logs for lockdown
parameters

Signed-off-by: Wonkyu Kim 
Change-Id: I63cec8a718285f424914e426d0399ed821588dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 231399c..78cfb9f 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -9,6 +9,7 @@
 #include <fsp/util.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/xdci.h>
+#include <intelpch/lockdown.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
@@ -97,6 +98,19 @@
    for (i = 0; i < 8; i++)
    	params->IomTypeCPortPadCfg[i] = 0x09000000;

+	/* Chipset Lockdown */
+	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
+		params->PchLockDownGlobalSmi = 0;
+		params->PchLockDownBiosInterface = 0;
+		params->PchUnlockGpioPads = 1;
+		params->RtcMemoryLock = 0;
+	} else {
+		params->PchLockDownGlobalSmi = 1;
+		params->PchLockDownBiosInterface = 1;
+		params->PchUnlockGpioPads = 0;
+		params->RtcMemoryLock = 1;
+	}
+
    /* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
    	params->PortUsb20Enable[i] = config->usb2_ports[i].enable;