[coreboot-gerrit] Change in ...coreboot[master]: stage_cache: Add into stage_cache if !CONFIG_NO_STAGE_CACHE

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33394

Change subject: stage_cache: Add into stage_cache if !CONFIG_NO_STAGE_CACHE
......................................................................

stage_cache: Add into stage_cache if !CONFIG_NO_STAGE_CACHE

Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534
Signed-off-by: Subrata Banik 
---
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/soc/intel/baytrail/refcode.c
M src/soc/intel/broadwell/refcode.c
4 files changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33394/1

diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 814bddf..a55df95 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -165,7 +165,8 @@
    	return;
    }

-	stage_cache_add(STAGE_REFCODE, fsp);
+	if (!CONFIG(NO_STAGE_CACHE))
+		stage_cache_add(STAGE_REFCODE, fsp);
 }

static int fsp_find_and_relocate(struct prog *fsp)
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index e72e4ac..ab9951d 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -128,7 +128,8 @@

prog_set_area(&fsps, dest, size);

-	stage_cache_add(STAGE_REFCODE, &fsps);
+	if (!CONFIG(NO_STAGE_CACHE))
+		stage_cache_add(STAGE_REFCODE, &fsps);

/* Signal that FSP component has been loaded. */
    prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 24469ea..daf3d1a 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -65,7 +65,8 @@
    }

/* Cache loaded reference code. */
-	stage_cache_add(STAGE_REFCODE, &prog);
+	if (!CONFIG(NO_STAGE_CACHE))
+		stage_cache_add(STAGE_REFCODE, &prog);

return prog_entry(&prog);
 }
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index 6d192cc..63decaf 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -61,7 +61,8 @@
    }

/* Cache loaded reference code. */
-	stage_cache_add(STAGE_REFCODE, &prog);
+	if (!CONFIG(NO_STAGE_CACHE))
+		stage_cache_add(STAGE_REFCODE, &prog);

return (pei_wrapper_entry_t)prog_entry(&prog);
 }