Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/27850
Change subject: soc/intel/apollolake: Add support for LPDDR4 nWR setting ......................................................................
soc/intel/apollolake: Add support for LPDDR4 nWR setting
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled.
BUG=b:112062440 TEST= build test
Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com --- M src/soc/intel/apollolake/include/soc/meminit.h M src/soc/intel/apollolake/meminit.c 2 files changed, 19 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27850/1
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 27b6556..adea59a 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -81,6 +81,7 @@ enum { ODT_A_B_HIGH_LOW = 0 << 1, ODT_A_B_HIGH_HIGH = 1 << 1, + nWR = 1 << 5, };
/* Provide bit swizzling per DQS and byte swapping within a channel. */ @@ -116,6 +117,7 @@ int ch1_dual_rank; const char *part_num; bool disable_periodic_retraining; + bool enable_nWR_24; };
struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index b0a5f4a..8690040 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -119,13 +119,6 @@ cfg->Ch1_Option = 0x3; cfg->Ch2_Option = 0x3; cfg->Ch3_Option = 0x3; - - /* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled - up to 1.1V. */ - cfg->Ch0_OdtConfig = ODT_A_B_HIGH_HIGH; - cfg->Ch1_OdtConfig = ODT_A_B_HIGH_HIGH; - cfg->Ch2_OdtConfig = ODT_A_B_HIGH_HIGH; - cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH; }
struct speed_mapping { @@ -326,6 +319,7 @@ const struct lpddr4_cfg *lpcfg, size_t sku_id) { const struct lpddr4_sku *sku; + u8 odt_config;
if (sku_id >= lpcfg->num_skus) { printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", @@ -358,6 +352,22 @@ }
cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; + + + /* + * Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled + * up to 1.1V. + * Set bit 5 in Ch0_OdtConfig to enable nWR24. + */ + if (sku->enable_nWR_24 == 1) + odt_config = ODT_A_B_HIGH_HIGH | nWR; + else + odt_config = ODT_A_B_HIGH_HIGH; + + cfg->Ch0_OdtConfig = odt_config; + cfg->Ch1_OdtConfig = odt_config; + cfg->Ch2_OdtConfig = odt_config; + cfg->Ch3_OdtConfig = odt_config; }
uint8_t fsp_memory_soc_version(void)