Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3004
-gerrit
commit fe9606cf3c184ad7fbaee518c51d622e43819e38 Author: Aaron Durbin adurbin@chromium.org Date: Mon Apr 1 15:33:02 2013 -0500
x86: add AUTO_CACHE_ROM_BSP option
When the AUTO_CACHE_ROM_BSP option is selected the ROM cache is automatically enabled for the BSP. That way, there doesn't need to be any other callers of x86_mtrr_enable_rom_caching() throughout the code base.
Change-Id: If236870ff7c3fd0cb317cbb80ee58cc9a266eeb0 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/cpu/x86/Kconfig | 7 +++++++ src/cpu/x86/mtrr/mtrr.c | 4 ++++ 2 files changed, 11 insertions(+)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 4c5176b..80bd2d7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -62,6 +62,13 @@ config CACHE_ROM When selected a variable range MTRR is allocated for coreboot and the bootloader enables caching of the system ROM for faster access.
+config AUTO_CACHE_ROM_BSP + bool + default n + depends on CACHE_ROM + help + Automatically enable ROM caching for the BSP. + config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6089127..c205da3 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -792,6 +792,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) commit_var_mtrrs(addr_space, mtrr_default_type, !!above4gb, address_bits); enable_var_mtrr(mtrr_default_type); +#if CONFIG_AUTO_CACHE_ROM_BSP + if (boot_cpu()) + x86_mtrr_enable_rom_caching(); +#endif enable_cache(); }